1. Field of the Invention
The present invention relates to a semiconductor device (hereafter, referred to as LSI) including a plurality of non-volatile memory macros. More particularly, the present invention relates to the LSI having a testing unit for effectively carrying out a verification (hereafter, referred to as verifying test) of an erasing operation and a writing operation of a non-volatile memory cell, which constitutes the memory macro and in which electrical erasing and writing are possible.
2. Description of the Related Art
At first, a memory cell of a non-volatile semiconductor memory device (Electrically Erasable and Programmable Read Only Memory; EEPROM), in which the electrical erasing and writing are possible, will be schematically described below. As is well known, the non-volatile memory cell includes a gate insulation film, a floating gate and a control gate on a semiconductor substrate. Under a condition that negative charges are not accumulated in the floating gate, if a positive voltage is applied to the control gate, a memory cell transistor is turned on. On the other hand, under a condition that negative charges are accumulated in the floating gate by injecting electrons therein, even if the positive voltage is applied to the control gate electrode, the memory cell is not immediately turned on. It is because the negative charges accumulated in the floating gate disable a channel to be immediately induced between a source and a drain. By further increasing the voltage applied to the control gate electrode and making it higher than a threshold voltage, the memory cell is turned on.
FIG. 1 is a diagram showing the typical example of the configuration of EEPROM of a collectively erasing type (also referred to as flash memory). With reference to FIG. 1, a memory cell array is composed of the plurality of memory cells MC which are arrayed in a shape of a matrix. The memory cell MC is a non-volatile memory cell. This memory cell array includes a plurality of word lines 508, a plurality of bit lines 509 and a plurality of source lines 510. Control gates of the memory cells on the same column are commonly connected to the word line 508. Drains of the memory cells on the same row are commonly connected to the bit line 509. Sources of the memory cells on the same column are commonly connected to the source line 510. The plurality of source lines 510 are commonly connected to each other, which is referred to as common source line 510. Incidentally, the following configuration of the memory cell array is used in many cases. The configuration is that the memory cell array is divided into a plurality of sectors, the sources of the plurality of memory cells within the same sector are connected to the common source line, and the collective erasing is performed on the sector unit.
The word lines 508 are connected to an X decoder 511, and the bit lines 509 are connected to an Y decoder 512.
The plurality of source lines 510, to which the sources of the respective memory cells are connected, are commonly connected and connected to a switching circuit 513. This switching circuit 513 connects them to a ground potential at the times of the reading and writing operations of the memory cell. It connects them to an erasing voltage generating circuit 514 at the time of the erasing operation of the memory cell.
Also, it includes a reading control circuit 515, a writing control circuit 516 and an erasing control circuit 517. The reading control circuit 515 is for carrying out a reading operation control of the memory cell. The writing control circuit 516 is for carrying out a writing control to the memory cell. The erasing control circuit 517 is for carrying out an erasing operation control of the memory cell. Respective control output signals from the reading control circuit 515, the writing control circuit 516 and the erasing control circuit 517 are sent to the X decoder 511 and the Y decoder 512, respectively.
FIGS. 2A and 2B are flowcharts showing an example of a procedure for a writing verification and an erasing verification of the flash memory. The operation of the conventional flash memory will be described below with reference to FIG. 1, FIGS. 2A and 2B.
When data is written to the memory cell, the common source line 510 is connected through the switching circuit 513 to the ground potential, thereby applying the ground potential to the source of the memory cell. Then, actuating the writing control circuit 516, a bit line selected by the Y decoder 512 is set at a high voltage, thereby applying the high voltage to the drain of the memory cell connected to the bit line. Also, a word line selected by the X decoder 511 is set at a high potential, thereby setting the control gate of the memory cell at a high voltage (for example, 12 V). Then, in the selected memory cell, hot electrons generated near the drain are injected into the floating gate (step S101–102 in FIG. 2A).
After that, as the procedure is shown in FIG. 2A, the writing state is set off (step S103), and the writing verifying operation is then started (step S104). That is, the data is read out from the memory cell corresponding to the writing address of the device (Step S105). Whether or not this read out data coincides with a certain writing data is verified (step S106). If the certain data is written (step S106: Yes) in the memory, the writing operation is ended. If the certain data is not written (step S106: No), the procedure returns back to the step S101, and the data is again written to the memory cell corresponding the same address.
When the data is read out, the common source line 510 is connected to the ground potential similarly to the time of the writing. Then, actuating the reading control circuit 515, the Y decoder 512 and the X decoder 511 set the bit line 509 and the word line 508 at the predetermined voltages, respectively. This sets the predetermined voltages for the gate and the drain of the memory cell, thereby reading out the data in the selected memory cell. At this time, the magnitude of the current flowing through the bit line 509 connected to the selected memory cell is detected by a sense amplifier (not shown). Consequently, “1” or “0” of the data stored in the selected memory cell is judged (in the following explanation, “1” and “0” indicate logical values, respectively).
Also, when the data is erased from the memory cell, the common source line 510 is connected through the switching circuit 513 to the erasing voltage generating circuit 514. Then, actuating the erasing control circuit 517, thereby the common source line 510 is set at a high potential (for example, 12 V). The sources of the memory cells are set at high potentials, all of the word lines 508 are set at the ground potential, all of the bit lines are set at open states, the drains of the memory cells are made open, and the collective erasing operation is performed on all of the memory cells (or the sector units) (Step S202). At this time, a strong electric field is generated between the source and the floating gate of the memory cell, and the electrons in the floating gate are pulled into the source side by the tunnel phenomenon.
In the flash memory, prior to the actual erasing operation, the writing operation of all the bits to be collectively erased are carried out in advance (at a step S201 of FIG. 2B) in order to make the thresholds of all the memory cells targeted for the collective erasing approximately equal to each other, typically. After that, so as not to bring about the over-erasing of the memory cell, the erasing verification is done in each of predetermined times, which the erasing time is finely divided into. In each of predetermined time unit, the erasing operation and then checking the thresholds of all the memory cells are carried out, little by little. Then, if a proper threshold is obtained, the erasing operation is stopped. That is, at an erasing state check mode, the data is read out from the device (Step S205), and whether or not the data is erased is verified (Step S206). If it is not erased, the erasing operation is again done only for a predetermined time (Step S202). On the other hand, if it is erased, whether or not an address on which the check for the erasing state is performed is a final address is checked. If it is not the final address, the procedure proceeds to a next address (Step S208), and the erasing state of the memory cell of the address is checked. On the other hand, if it is the final address, the erasing operation is completed.
If the erasing time becomes a certain value or more, a threshold voltage of the memory cell, which is, for example, written at a threshold voltage of about 5 V at an initial state, becomes negative. This memory cell is at a depression state at which it is turned on even if its gate potential is the ground potential. If the over-erasing condition is induced, a right data can not be read out. For example, in the memory cell array shown in FIG. 1, under the situation that a memory cell H is in the over-erasing condition, if a data is written to a memory cell J and this data is further read out, a current does not flow between a drain and a source in the selected memory cell J. However, a current flows between a drain and a source in the non-selected memory cell H. For this reason, a current flows through a bit line B1, and the sense amplifier detects the memory cell J, which is an off bit, as the on bit. Thus, in order to avoid such over erasing condition from being induced, the procedure for repeating the collective erasing operation at the predetermined time unit and the erasing verification for each address after that is carried out as mentioned above. The erasing verification requires a very long time as compared with the reading out operation and the writing verification.
That is, in the conventional flash memory, the operational time is long in the order of the reading out operation, the writing operation including the verification and the erasing operation including the verification. For example, the reading out operation requires the time of the order of 100 ns (nano-seconds). The writing operation including the verification requires the time of the order of several ten is (micro seconds). The erasing operation including the verification requires the time of the order of several hundred ms (mili-seconds). For this reason, in association with the increase in a memory capacity, the test time involving the verifying operation becomes longer.
The LSI, such as a micro processor which includes the non-volatile memory such as the flash memory and the like and CPU (Central Processing Unit) on the same substrate, is given to a user in the shape that the non-volatile memory is divided into a plurality of memory blocks (memory macros). This is for treating with the increase in a necessary memory capacity and the various applications on the user side. The non-volatile memory built in a microcomputer typically stores therein a program to be executed in the CPU and data and the like. For example, it is designed such that the manufacturing side preliminarily prepares four memory blocks (the maximum of 4 M bits), each having 8 bits×128 K (=1 M bits). The configuration of the usage memory blocks can be varied in response to the application on the user side. This reason is as follows. That is, in association with the increase in the memory capacity, if one memory cell array is composed of many memory cells which have large capacity, for example, the increase in the number of cell transistors, in which each drain is connected to one bit line, increases the load. Moreover, in association with the increases in a wire resistance and a wire capacitance, it is difficult to uniformly transmit a signal from one end of the bit line to a cell transistor located at another end. That is, the non-volatile memory is divided in advance into the plurality of memory blocks, and the memory blocks are used corresponding to the necessary capacity. This realizes the large memory capacity and a high speed access simultaneously.
Incidentally, if the LSI having the plurality of non-volatile memory blocks is designed so as to output in parallel the output data of the respective memory blocks in their original states from test terminals to outside, the number of the output terminals dedicated to the test which are mounted on the LSI is increased proportionally to the number of the memory blocks. Thus, this is inefficient and uneconomical. In particular, in the case of the multiple-bit structure in which the non-volatile memory block has 4 bits, 8 bits and the like, the number of the output terminals dedicated to the test is increased. Hence, the structure in which the output data of the respective memory blocks are outputted in their original states and in parallel from the terminals for the test to the outside is not actually used from the viewpoints of the restriction on the number of the terminals and the cost.
Conventionally, for example, the LSI, which includes the plurality of non-volatile memory blocks in the multiple-bit structure as mentioned above, uses the structure shown in FIG. 3.
FIG. 3 is a view showing an example of a configuration of a conventional microprocessor. This microprocessor 600 has a plurality of memory blocks of a flash type EEPROM on the same substrate. With reference to FIG. 3, this micro processor 600 includes memory blocks 601_1 to 601_3 composed of flash memories with the multiple-bit structure of the same bit width (n-bit width; n is an integer of 2 or more). It also includes a selector 604 whose inputs are connected to data buses 603_1 to 603_3 to transfer output data from the memory blocks 601_1 to 601_3. The output data (n bits) of the memory block selected by the selector 604 is outputted to a data output terminal 605.
When the writing verifying or erasing verifying test is executed, an address signal sent by an automatically testing apparatus (not shown) is sent as a read address from an address bus 602 to the memory blocks 601_1 to 601_3. The output data from the memory block selected by the selector 604 is outputted to the data output terminal 605, and the output data is sent to a comparator of a pin electronics card of the automatically testing apparatus (not shown). A selection signal for controlling the selection of the selector 604 is sent by the automatically testing apparatus (not shown). On the other hand, at a time of a usual operation, the data read out from the memory blocks 601_1 to 601_3 on the basis of the read address from CPU (not shown) is sent as a read data to the CPU. The data output terminal 605 is an outer terminal dedicated to the test, and the number of the data output terminals 605 corresponds to the bit width of the output data of the memory block.
However, such as this LSI, the configuration, in which the terminal number of the outer terminals dedicated to the test is limited by the mechanism that the output data from the plurality of non-volatile memory blocks are selected by the selector and outputted from the output terminals, has the problem of the remarkable increase in the test time of the LSI including the non-volatile memory blocks, as a result.
FIG. 4 is a flowchart showing an example of a test sequence usually carried out in the test of the flash memory. In this case, at first, a test 1 carries out the erasing operation and the erasing verification (Steps S301, S302). At this time, if the erasing verification is impossible (failed), the erasing operation is again carried out as mentioned above.
If the erasing verification is passed, a test 2 carries out the writing operation of a checker pattern and the writing verification (Steps S303, S304).
If the writing verification is passed, a test 3 carries out the erasing operation and the erasing verification (Steps S305, S306).
Next, a test 4 carries out the writing operation of a checker bar pattern and the writing verification (Steps S307, S308). If the writing verification is passed, a test 5 again carries out the erasing operation and the erasing verification (Steps S309, S310).
Next, a test 6 carries out the writing operation of all “0” data and the writing verification (Steps S311, S312).
Then, after a test 7 carries out a burn-in (wafer baking), the writing verification is again carried out (Steps S313, S314). Again, a test 8 carries out the erasing operation and the erasing verification (Steps S315, S316).
If the test composed of the test sequences as mentioned above is executed to the LSI shown in FIG. 3 as the device to be tested, since the LSI is designed that the output data selected by the selector 604 among the memory blocks 601_1 to 601_3 is outputted from the data output terminal 605, the verifying operations can not be performed in parallel between the memory blocks 601_1 to 601_3. That is, because of the restriction on the number of the terminals, it is designed such that the output data of the memory block is selected by the selector 604 and outputted to the outer terminal. Hence, when the data necessary for the verifying operation is read out, the read data of the plurality of memory blocks can not be outputted to the outside at the same time.
For this reason, when the verifying test is carried out at the testing step of the conventional LSI, the selector 604 sequentially switches the output data of the memory blocks 601_1 to 601_3, and outputs to the data output terminal 605. Then, the comparator of the automatically testing apparatus compares it with an expectation value, thereby judging a pass or a failure. In association with the increase in the memory capacity of the memory blocks built in the LSI and the increase in the number of the memory cell blocks, the verification test time is increased.
As the means to solve the above-mentioned problems, the inventor of the present invention proposes LSI in Japanese Laid Open Patent Application (JP-A 2001-155500). It is possible for the proposed LSI to shorten the test time for the verifying test and the like, while suppressing the increase in the number of the terminals dedicated to the test, even in the LSI having the plurality of non-volatile memory macros.
FIG. 5A is a view showing the schematic configuration of one example of the LSI disclosed in the above-mentioned patent application. With reference to FIG. 5A, an LSI 700 includes flash memory blocks (hereafter, referred to as memory macro) 701_1 to 701_3, an address bus 702, output data buses 703_1 to 703_3, verifying circuits 705_1 to 705_3, verification result output terminals 706_1 to 706_3, expectation value data input terminal 707, an address bus 708, a data bus 709, selectors 710, 712 and 713, an address input terminal 714, a data input terminal 715 and a CPU 720.
The flash memory blocks 701_1 to 701_3 are three non-volatile memory blocks, and output data from the respective memory blocks 701_1 to 701_3 are outputted to output data buses 703_1 to 703_3, respectively. These data are inputted to verifying circuits 705_1 to 705_3, respectively. Data of plural (n-) bit width are outputted as read data from the respective memory blocks 701_1 to 701_3, and the output data buses 703_1 to 703_3 are defined as the n-bit width.
FIG. 5B is a view showing the schematic configuration of the verifying circuits disclosed in the above-mentioned patent application. Each of the verifying circuits 705_1 to 705_3 includes: n exclusive logical sum gates EXOR_1 to EXOR_n and a logical sum gate OR. Each of the n exclusive logical sum gates EXOR_1 to EXOR_n compares each bit data of the output data buses 703_1 to 703_3 of the n-bit width with each bit data of an expectation value data 704 of the n-bit width input from an expectation value data input terminal 707. Then, it judges whether or not they are coincident with each other. The logical sum gate OR carries out the logical sum between the outputs of the n exclusive logical sum gates EXOR_1 to EXOR_n. Then, it outputs verification result judgment signals to verification result output terminals 706_1 to 706_3. In the LSI 700, the verification result output terminals 706_1 to 706_3 are placed correspondingly to the number of the memory blocks 701_1 to 701_3, and the verification result judgment signals from the respective verifying circuits 705_1 to 705_3 are outputted to the automatically testing apparatus (not shown), in parallel to each other.
When the LSI 700 is tested, the writing verification and erasing verification tests are carried out in parallel in the three memory blocks 701_1 to 701_3. That is, the same read address is sent from the side of the automatically testing apparatus (not shown) to the three memory blocks 701_1 to 701_3. Each of the verifying circuits 705_1 to 705_3 compares the read data outputted from each of the memory blocks 701_1 to 701_3 with the expectation value data sent to the expectation value data input terminal 107 from the automatically testing apparatus (not shown), every bit unit. Then, if there is the bit data that does not coincide with the expectation value data, namely, if the output signal from any one of the exclusive logical sum gates EXOR is “1”, the verification result judgment signal outputted from the logical sum gate OR is “1”. Consequently, the LSI 700 itself can carry out the verification. The comparator of the automatically testing apparatus (not shown) is connected to the verification result output terminals 706_1 to 706_3. The automatically testing apparatus judges it as the pass if the verification result judgment signal from each of the verifying circuits 705_1 to 705_3 is “0”, and judges it as the fail if it is “1”.
Thus, for example, when each memory block has an 8-bit data output (the bit width of the data bus n=8), in order to make the speed of the verifying test faster, if the circuit is configured so as to output the data of the three memory blocks (the number of the memory blocks m=3) in parallel, this configuration requires 24 (=m×n) output terminals dedicated to the test. Moreover, this configuration requires 24 comparators of the automatically testing apparatus. However, according to the LSI 700, although the time necessary for the test is not changed, as the necessary output terminal dedicated to the test, it is enough to mount the three verification result output terminals 706_1 to 706_3 corresponding to the number (3) of the memory blocks. Thus, the number of the output terminals dedicated to the test is extremely reduced. Hence, the number of the comparators necessary for the verifying test may be three in the automatically testing apparatus.
As mentioned above, in the LSI based on the above patent application, while the time necessary for the writing verifying test and the erasing verifying test is kept equal to that in the case of the circuit configuration of outputting the data of each memory macro as all-bit parallel, the number of the output terminals dedicated to the test for the verifying test of each memory macro is greatly reduced to the number equal to the number of the memory macros built in the LSI.
However, in recent years, the number of the non-volatile memory macros built in the LSI has been increased, and the structure of the memory macro (the number of the memory cells included in one memory macro) has been diversified. In particular, the method of carrying out the plurality of memory macro verifying tests, in which memory sizes are different, in parallel at the same time, without any increase in the number of the terminals dedicated to the test is not attained up to the present. It is desired to further improve the efficiency of the verifying test of the memory macro whose structure is diversified, while suppressing the increase in the number of the terminals dedicated to the test.